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asahi kasei [AK5366VR] ms0526-e-00 2006/07 - 1 - general description AK5366VR is a high-performance 24-bi t, 48khz sampling adc for consum er audio and digital recording applications. thanks to akm?s enhanced dual-bit modulator architecture, this analog-to-digital converter has an impressive dynamic range of 103db with a high level of integrat ion. the AK5366VR has a 5-channel stereo input selector, an i nput programmable gain amplifier with an alc function. all this integration with high-performance makes the ak5366v r well suited for cd and dvd recording systems. features 1. 24bit stereo adc ? 5ch stereo inputs selector ? input pga from +18db to 0db, 0.5db step ? peak hold function ? auto level control (alc) circuit ? digital hpf for offset cancellation (fc=1.0hz@fs=48khz) ? digital attenuator from +8db to ? 63db, mute ? soft mute ? single-end inputs ? s/(n+d) : 94db ? dr, s/n : 103db ? audio i/f format : 24bit msb justified, i 2 s 2. 3-wire serial p interface / i 2 c-bus 3. master / slave mode 4. master clock : 256fs/384fs/512fs 5. sampling rate : 32khz to 48khz 6. power supply ? avdd: 4.75 5.25v (typ. 5.0v) ? dvdd: 3.0 5.25v (typ. 3.3v) ? tvdd: 3.0 5.25v for input tolerant (typ. 5.0v) 7. ta = ? 40 85 c 8. package : 48pin lqfp (7mm x 7mm) 24-bit 48khz ? adc with selector/pga/alc AK5366VR
asahi kasei [ak5366v r] ms0526-e-00 2006/07 - 2 - ? block diagram lin1 lin2 lin3 lin4 lin5 rin1 rin2 rin3 rin4 rin5 adc ipgal ropin rout ipgar control register i/f csn cad1 cclk scl cdti sda lopin m/s pdn lout ipga ipga i2c (alc) (alc) smute pre-amp pre-amp hpf datt peak hold vcom tvdd lrck bick mclk sdto avss avdd dvss dvdd audio i/f controller sel2 sel1 sel0 block diagram
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 3 - ? ordering guide AK5366VR ? 40 +85 c 48pin lqfp (0.5mm pitch) akd5366vr evaluation board for AK5366VR ? pin layout 1 lin5 2 test1 3 lin4 4 test2 5 6 test3 7 8 lin2 9 10 test4 11 lin1 12 nc lopin lout rin5 test8 rin4 48 test7 47 rin3 46 45 test6 44 rin2 43 test5 42 rin1 41 nc 40 m/s i2c 17 nc 18 ipga r 19 rout 20 ropin 21 22 nc 23 24 avdd avss vcom dvss dvdd sdto csn/cad1 cclk/scl sdti/sda 36 sel2 35 34 sel1 33 sel0 32 31 30 29 smute 28 tvdd 27 pdn mclk top view 14 15 16 lrck 13 26 25 39 38 37 lin3 ipgal bick AK5366VR
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 4 - ? compatibility with ak5365 ak5365 ak5366 AK5366VR fs max. 96khz max. 48khz alc bit default value ?0? : alc=off ?1? : alc=on ipgl/r7-0 default value ?7fh? : 0db ?80h? : 0db ref7-0 bit default value ?89h? : +4.5db ?8eh? : +7.0db ipga gain 0db +12db 0db +18db datt volume ? 72db 0db ? 63db +8db mclk ac coupling input no yes peak hold circuit no yes i2c speed 100khz 400khz 5v tolerant no yes package 44pin lqfp 48pin lqfp software compatibility addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down & reset control 0 0 0 0 0 mckpd mckac pwn 01h input selector control 0 0 0 0 0 sel2 sel1 sel0 02h clock & format control 0 0 0 0 dif cks1 cks0 smute 03h timer select 0 0 ltm1 ltm0 ztm1 ztm0 wtm1 wtm0 04h lch ipga control ipgl7 ipgl6 ipg l5 ipgl4 ipgl3 ipgl2 ipgl1 ipgl0 05h rch ipga control ipgr7 ipgr6 ipgr5 ipgr4 ipgr3 ipgr2 ipgr1 ipgr0 06h alc mode control 1 0 0 zelmn alc fr lmth ratt lmat 07h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 08h lch datt control attl7 attl6 attl5 attl7 attl7 attl7 attl7 attl0 09h rch datt control attr7 attr6 attr5 attr4 attr3 attr2 attr1 attr0 0ah lch peak hold low byte phl7 phl6 phl5 phl4 phl3 phl2 phl1 phl0 0bh lch peak hold high byte phl15 phl14 phl13 phl12 phl11 phl10 phl9 phl8 0ch rch peak hold low byte phr7 phr6 phr5 phr4 phr3 phr2 phr1 phr0 0dh rch peak hold high byte phr15 phr14 phr13 phr12 phr11 phr10 phr9 phr8 : changing points from ak5365?s register.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 5 - pin/function no. pin name i/o function 1 lin5 i lch analog input 5 pin 2 test1 i test 1 pin this pin should be connected to avss. 3 lin4 i lch analog input 4 pin 4 test2 i test 2 pin this pin should be connected to avss. 5 lin3 i lch analog input 3 pin 6 test3 i test 3 pin this pin should be connected to avss. 7 lin2 i lch analog input 2 pin 8 test4 i test 4 pin this pin should be connected to avss. 9 lin1 i lch analog input 1 pin 10 nc - no internal bonding. connect to gnd. 11 lopin i lch feedback resistor input pin 12 lout o lch feedback resistor output pin 13 ipgal i lch ipga input pin 14 nc - no internal bonding. connect to gnd. 15 ipgar i rch ipga input pin 16 rout o rch feedback resistor output pin 17 ropin i rch feedback resistor input pin 18 nc - no internal bonding. connect to gnd. 19 avdd - analog power supply pin, 4.75 5.25v 20 avss - analog ground pin 21 vcom o common voltage output pin, avdd/2 bias voltage of adc input. 22 dvss - digital ground pin 23 dvdd - digital power supply pin, 3.0 5.25v 24 sdto o audio serial data output pin note: all digital input pins except pull-down pins should not be left floating. note: test1, test2, test3 and test4 pins should be connected to avss.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 6 - no. pin name i/o function 25 bick i/o audio serial data clock pin 26 lrck i/o output channel clock pin 27 mclk i master clock input pin 28 pdn i power-down mode pin ?h?: power up, ?l?: power down reset and initializes the control register. 29 tvdd - input buffer power supply pin, 3.0 5.25v 30 smute i soft mute pin (internal pull-down pin, typ. 100k ? ) ?h? : soft mute, ?l? : normal operation 31 sel0 i input selector 0 pin 32 sel1 i input selector 1 pin 33 sel2 i input selector 2 pin cdti i control data input pin in 3-wire control (i2c pin = ?l?) 34 sda i/o control data input / output pin in i 2 c control (i2c pin = ?h?) cclk i control data clock pin in 3-wire control (i2c pin = ?l?) 35 scl i control data clock pin in i 2 c control (i2c pin = ?h?) csn i chip select pin in 3-wire c ontrol (i2c pin = ?l?) 36 cad1 i chip address 1 select pin in i 2 c control (i2c pin = ?h?) 37 i2c i control mode pin ?h? : i 2 c control , ?l? : 3-wire control 38 m/s i master / slave mode pin ?h? : master mode, ?l? : slave mode 39 nc - no internal bonding. connect to gnd. 40 rin1 i rch analog input 1 pin 41 test5 i test 5 pin this pin should be connected to avss. 42 rin2 i rch analog input 2 pin 43 test6 i test 6 pin this pin should be connected to avss. 44 rin3 i rch analog input 3 pin 45 test7 i test 7 pin this pin should be connected to avss. 46 rin4 i rch analog input 4 pin 47 test8 i test 8 pin this pin should be connected to avss. 48 rin5 i rch analog input 5 pin note: all digital input pins except pull-down pins should not be left floating. note: test5, test6, test7 and test8 pins should be connected to avss.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 7 - ? handling of unused pin the unused input pins should be processed appropriately as below. classification pin name setting lin1-5 rin1-5 ipgal ipgar these pins should be open. analog lopin/lout ropin/rout connected 10k ? resistor between lopin pin and lout pin. connected 10k ? resistor between ropin pin and rout pin. digital smute sel2-0 csn cclk/scl cdti/sda i2c these pins should be connected to dvss.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 8 - absolute maximum ratings (avss, dvss=0v; note 1 parameter symbol min max units power supplies: analog digital input buffer (note 2) |avss ? dvss| (note 3) avdd dvdd tvdd ? gnd ? 0.3 ? 0.3 ? 0.3 - 6.0 6.0 6.0 0.3 v v v v input current, any pin except supplies iin - 10 ma analog input voltage (note 4) (lin1-5, rin1-5, lopin, ropin, ipgal, ipgar, m/s pins) vina ? 0.3 avdd+0.3 v digital input voltage 1 (mclk, bick, lrck, pdn pins) vind1 ? 0.3 dvdd+0.3 v digital input voltage 2 (smute, sel2-0, csn/cad1, cclk/scl, cdti/sda, i2c pins) vind2 ? 0.3 tvdd+0.3 v ambient temperature (powered applied) ta ? 40 85 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. smute, sel2-0, csn/cad1, cclk/scl, cdti/sda and i2c pins correspond to 5v tolerant. note 3. avss and dvss must be connected to the same analog ground plane. note 4. m/s pin is the digital input pin. however, m/s pin should be connected to avdd or avss to prevent the noise to the analog input pins warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v; note 1) parameter symbol min typ max units power supplies (note 5) analog digital input buffer avdd dvdd tvdd 4.75 3.0 dvdd 5.0 3.3 5.0 5.25 avdd avdd v v v note 1. all voltages with respect to ground. note 5. the power up sequence betw een avdd, dvdd and tvdd is not critical. warning: akm assumes no responsibility for the us age beyond the conditions in this datasheet.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 9 - analog characteristics (ta=25 c; avdd=tvdd=5.0v, dvdd=3.3v; avss=dvss=0v; fs=48khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz at fs=48khz; unless otherwise specified) parameter min typ max units pre-amp characteristics: feedback resistance 10 50 k ? s/(n+d) (note 6) - 100 db s/n (a-weighted) (note 6) - 108 db load resistance (note 7) 6.3 k ? load capacitance 20 pf input pga characteristics: input voltage (note 8) 0.9 1 1.1 vrms input resistance (note 9) 6.3 10 15 k ? step size 0.2 0.5 0.8 db gain control range alc = off alc = on 0 ? 9.5 +18 +18 db db adc analog input characteristics: ipga=0db, alc = off (note 10) resolution 24 bits s/(n+d) ( ? 0.5dbfs) 84 94 db dr ( ? 60dbfs, a-weighted) 96 103 db s/n (a-weighted) 96 103 db interchannel isolation (note 11) 90 110 db interchannel gain mismatch 0.2 0.5 db gain drift 100 - ppm/ c power supply rejection (note 12) 50 - db power supplies power supply current normal operation (pdn pin = ?h?) avdd dvdd+tvdd power-down mode (pdn pin = ?l?) (note 13) avdd dvdd+tvdd 23 4 10 10 35 8 100 100 ma ma a a note 6. this value is measured at lout and rout pins using the circuit as shown in figure 25. the input signal voltage is 2vrms. note 7. this value is the input impedance of an external device that the lout and rout pins can drive, when a device is connected with lout and r out pin externally. the feedback resistor (min. 10k ? ) that it is usually connected with the lout/rout pins, and the value of input impedance (min. 6.3k ? ) of the ipgal/r pins are not included. note 8. full scale (0db) of the input voltage at alc=off and ipga=0db. input voltage to ipgal and ipgar pins is proportional to avdd voltage. typ. vin = 0.2 x avdd (vrms). note 9. this value is input impedance of the ipgal and ipgar pins. note 10. this value is measured via the following path. pre-amp ipga (gain : 0db) adc. the measurement circuit is figure 25. note 11. this value is the interchannel isolation between all the channels of the lin1-5 and rin1-5 when the applied input signal causes the pre-amp output to equal ipga input. note 12. psr is applied to avdd, dvdd and tvdd with 1khz, 50mvpp. note 13. all digital input pins are held dvss.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 10 - filter characteristics (ta= ? 40 85 c; avdd=4.75 5.25v; dvdd, tvdd=3.0 5.25v; fs=48khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 14) ? 0.005db ? 0.02db ? 0.06db ? 6.0db pb 0 - - - 21.768 22.0 24.0 21.5 - - - khz khz khz khz stopband sb 26.5 khz passband ripple pr 0.005 db stopband attenuation sa 80 db group delay (note 15) gd 31 1/fs group delay distortion ? gd 0 s adc digital filter (hpf): frequency response (note 14) ? 3db ? 0.5db ? 0.1db fr 1.0 2.9 6.5 hz hz hz note 14. the passband and stopband frequencies scale with fs. for example, 21.768khz at ? 0.02db is 0.454 x fs. note 15. the calculated delay time induced by digital f iltering. this time is from the input of an analog signal to the setting of 24bit data both channels to the adc output register for adc. dc characteristics (ta= ? 40 85 c; avdd=4.75 5.25v; dvdd, tvdd=3.0 5.25v) parameter symbol min typ max units high-level input voltage (note 16) low-level input voltage (note 16) input voltage at ac coupling (note 17) vih vil vac 70%dvdd - 50%dvdd - - - 30%dvdd - v v v high-level output voltage (iout= ? 400 a) low-level output voltage (except sda pin : iout=400 a) (sda pin : iout=3ma) voh vol vol dvdd ? 0.5 - - - - - - 0.5 0.4 v v v input leakage current (note 18) iin - - 10 a note 16. smute, sel2-0, csn/cad1, cclk/scl, cdti/sda and i2c pins correspond to 5v tolerant. note 17. when ac coupled capacitor is connected to mclk pin. note 18. smute pin is internally connected to a pull-down resistor. (typ. 100k ? )
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 11 - switching characteristics (ta= ? 40 85 c; avdd=4.75 5.25v; dvdd, tvdd=3.0 5.25v; c l =20pf) parameter symbol min typ max units master clock timing frequency pulse width low pulse width high ac pulse width (note 19) fclk tclkl tclkh tacw 8.192 0.3/fclk 0.3/fclk 0.4/fclk 24.576 mhz ns ns ns lrck frequency frequency fsn 32 48 khz duty cycle slave mode master mode 45 50 55 % % audio interface timing slave mode bick period bick pulse width low pulse width high lrck edge to bick ? ? (note 20) bick ? ? to lrck edge (note 20) lrck to sdto (msb) (except i 2 s mode) bick ? ? to sdto tbck tbckl tbckh tlrb tblr tlrs tbsd 160 65 65 30 30 35 35 ns ns ns ns ns ns ns master mode bick frequency bick duty bick ? ? to lrck bick ? ? to sdto fbck dbck tmblr tbsd ? 20 ? 20 64fs 50 20 35 hz % ns ns note 19. pulse width to ground level when mclk is connected to a capacitor in series and a resistor is connected to ground. note 20. bick rising edge must not occur at the same time as lrck edge.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 12 - parameter symbol min typ max units control interface timing (3-wire serial mode): cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note 21) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 400 - - - - - - - 0.3 0.3 - 50 khz s s s s s s s s s s ns reset timing pdn pulse width (note 22) pdn ? ? to sdto valid (note 23) csn ? ? to sdto valid (note 24) tpd tpdv tpdv 150 516 516 ns 1/fs 1/fs note 21. data must be held long enough to bridge the 300ns-transition time of scl. note 22. the AK5366VR can be reset by bringing the pdn pin = ?l?. note 23. this cycle is the number of lrck rising edges from the pdn pin = ?h?. note 24. this cycle is the number of lrck rising edges from the csn = ?h?. purchase of asahi kasei microsystems co., ltd i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system, provided the sy stem conform to the i 2 c specifications defined by philips.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 13 - ? timing diagram 1/fclk mclk tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil clock timing mclk input measurement point a gnd tacw t acw a gnd 1/fclk 1000pf 100k ? vac mclk ac coupling timing (measurement condition) *refer to figure 2 for input circuit example.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 14 - lrck vih vil tblr bick vih vil tlrs sdto 50%dvdd tlrb tbsd audio interface timing (slave mode) lrck bick 50%dvdd sdto 50%dvdd tbsd tmblr dbck 50%dvdd audio interface timing (master mode) csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w write command input timing
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 15 - csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2 write data input timing stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp i 2 c bus mode timing tpd pdn vil csn vih vil tpdv sdto 50%dvdd pdn vih vil tpdv sdto 50%dvdd power down & reset timing
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 16 - operation overview ? system clock mclk (256fs/384fs/512fs), bick (48fs ) and lrck (fs) clocks are required in slave mode. the lrck clock input must be synchronized with mclk, however the phase is not critical. mclk frequency is automatically detected in slave mode. table 1 shows the relationship of typical sampling frequency and the system clock frequency. setting of cks 1-0 bit is ignored. mclk (256fs/384fs/512fs) is required in master mode. mclk freque ncy is selected by cks1-0 bits as shown in table 2. in master mode, after setting cks1-0 bits, there is a possibility the frequency and duty of lrck and bick outputs become an abnormal state. all external clocks (mclk, bick and lrck) must be pres ent unless pdn pin = ?l? and pwn bit = ?1?. if these clocks are not provided, the AK5366VR may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the AK5366VR in power-down mode (pdn pin = ?l? or pwn bit = ?0?). in master mode, the master clock (mclk) must be provided unless pdn pin = ?l?. mclk fs 256fs 384fs 512fs 32khz 8.192mhz 12.288mhz 16.384mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 48khz 12.288mhz 18.432mhz 24.576mhz table 1. system clock example (slave mode) cks1 cks0 mclk 0 0 256fs default 0 1 512fs 1 0 384fs 1 1 n/a table 2. master clock frequency select (master mode)
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 17 - [mclk ac coupling input] mclk ac coupling input beco mes possible by controlling mckpd bit and mckac bit. master clock status mckac bit mckpd bit clock is input to mclk pin. 0 0 external clock direct input (figure 1) clock isn?t input to mclk pin. 0 don?t care clock is input to mclk pin. 1 0 ac coupling input (figure 2) clock isn?t input to mclk pin. 1 1 table 3. mckpd bit and mckac bit setting for master clock status (1) external clock direct input mclk AK5366VR mckpd = "0" external clock mckac = "0" figure 1. external master clock input block (2) ac coupling input mclk AK5366VR mckpd = "0" external clock mckac = "1" c figure 2. external clock mode (input : 50%dvdd, input circuit example) - note: this clock level must not exceed dvdd level. (c : 0.1 f) ? audio interface format two kinds of data formats can be chosen with the dif bit (table 4). in both modes, the serial data is in msb first, 2?s compliment format. the sdto is clocked out on the falling e dge of bick. the audio interface supports both master and slave modes. in master mode, bick and lrck are output with the bick frequency fixed to 64fs and the lrck frequency fixed to 1fs. mode dif bit sdto lrck bick figure 0 0 24bit, msb justified h/l 48fs (slave) 64fs (master) figure 3 default 1 1 24bit, i 2 s compatible l/h 48fs (slave) 64fs (master) figure 4 table 4. audio interface format
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 18 - lrck bick(64fs) sdto(o) 0 23 22 1 2 4 0 20 21 24 31 0 12 23 22 0 1 0 23 22 20 21 31 23:msb, 0:lsb lch data rch data 24 321 22 23 23 1 2 3 4 figure 3. mode 0 timing lrck bick(64fs) sdto(o) 0 23 22 1 2 4 0 25 21 24 0 12 23 22 0 1 0 22 25 21 24 321 22 23 23 1 2 3 4 3 23:msb, 0:lsb lch data rch data figure 4. mode 1 timing ? master mode and slave mode the m/s pin selects either master or slave mode. m/s pin = ?h? selects master mode and ?l? selects slave mode. the AK5366VR outputs bick and lrck in master mode. in slave mode, mclk, bick and lrck are input externally. bick, lrck slave mode bick = input lrck = input master mode bick = output lrck = output table 5. master mode/slave mode ? digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is 1.0hz (@fs=48khz) and scales with sampling rate (fs).
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 19 - ? power-up/down the AK5366VR is placed in the power-down mode by bringing p dn pin = ?l? and the digital filter is also reset at the same time. this reset should always be done after power- up. an analog initialization cy cle starts after exiting the power-down mode. therefore, the output data sdto becomes available after 516 cycles of lrck. power supply pdn pin a dc internal state a lc bit a lc function ipga sdto external clocks in slave mode external clocks in master mode bick, lrck in master mode 150ns pdn ?0? fixed to ?l? inita unknown on ?1? normal ?0? off (1) output mclk, bick, lrck input mclk input bick, lrck output the clocks can be stopped. ? pdn : power down state. ? inita : initializing period of adc analog section (516/fs). ? (1) : after alc operation is disabled, the ipga changes to the last written data during or before alc operation. figure 5. power-up sequence ? peak hold circuit the AK5366VR includes the peak hold circuit. the peak is held l/r audio data independently. these registers are reset by reading 8bit of msb, reading 8bit of both msb and lsb should be continuity controlled by reading in order of 8bit of msb from lsb. after reading 8bit of lsb the last, 8bit of msb is lost by reading 8bit of lsb the last. the output value is the absolute value. full scale is ?ffffh?.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 20 - ? input selector the AK5366VR includes 5ch stereo input selectors (figure 6). the input selector is 5 to 1 selector. the input channel is set by the sel2-0 bits (table 6) and the sel2-0 pins (t able 7). the sel2-0 pins should be fixed to ?lll? if the AK5366VR is controlled by the sel 2-0 bits, because the setting of the sel2-0 pins are prior to the sel2-0 bits setting. sel2 bit sel1 bit sel0 bit input channel 0 0 0 lin1 / rin1 default 0 0 1 lin2 / rin2 0 1 0 lin3 / rin3 0 1 1 lin4 / rin4 1 0 0 lin5 / rin5 table 6. input selector (sel2-0 pin = ?lll?) sel2 pin sel1 pin sel0 pin input channel l l l lin1 / rin1 l l h lin2 / rin2 l h l lin3 / rin3 l h h lin4 / rin4 h l l lin5 / rin5 table 7. input selector (sel2-0 bit = ?000?) lin1 lin2 lin3 lin4 lin5 rin1 rin2 rin3 rin4 rin5 pre-amp pre-amp figure 6. input selector
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 21 - [input selector switching sequence] the input selector should be changed after soft mute to avoid the switching noise of the input selector (figure 7). 1. enable the soft mute before changing channel. 2. change channel. 3. disable the soft mute. smute a ttenuation channel datt level - (1) (2) lin1/rin1 lin2/rin2 (1) figure 7. input channel switching sequence example the period of (1) varies in the setting value of datt. it takes 1028/fs to mute when datt value is +8db. when changing channels, the input channel should be ch anged during (2). the period of (2) should be around 200ms because there is some dc di fference between the channels.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 22 - ? input attenuator the input atts are constructed by adding the input resistor (ri) for lin1-5/rin1-5 pins and the feedback resistor (rf) between lopin (ropin) pin and lout (rout) pin (figure 8) . the input voltage range of the ipgal/ipgar pin is typically typ. 0.2 x avdd (vrms). if the i nput voltage of the input selector exceed s typ. 0.2 x avdd, the input voltage of the ipgal/ipgar pins must be attenuated to 0.2 x avdd by the input atts. table 8 shows the example of ri and rf. lin1 lin2 lin3 lin4 lin5 rin1 rin2 rin3 rin4 rin5 ipgal ropin rout ipgar lopin lout pre-amp pre-amp to ipga to ipga ri ri ri ri ri ri ri ri ri ri rf rf figure 8. input att ? example for input range input range ri [k ? ] rf [k ? ] att gain [db] ipgal/r pin 4vrms 47 12 ? 11.86 1.02vrms 2vrms 47 24 ? 5.84 1.02vrms 1vrms 47 47 0 1vrms table 8. input att example
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 23 - ? input volume the AK5366VR includes two independent channel analog volumes (ipga) with 37 levels at 0.5db steps located in front of the adc. the ipga is a true analog volume control that improves the s/n ratio as seen in table 9. independent zero-crossing detection is used to ensure level changes only occur duri ng zero-crossings. if there are no zero-crossings, the level will then change after a time-out period (table 10); the time-out period scales with fs. if a new value is written to the ipga register before the ipga changes at the zero crossing or tim e-out, the previous value becomes invalid. the timer (channel independent) for time-out is reset and th e timer restarts for new ipga value. input gain setting 0db +6db +18db fs=48khz, a-weight 103db 100db 89db table 9. pga+adc s/n ztm1 ztm0 zero crossing timeout period @fs=48khz 0 0 288/fs 6ms 0 1 1152/fs 24ms 1 0 2304/fs 48ms default 1 1 4608/fs 96ms table 10. zero crossing timeout period [writing operation at alc enable] writing to the area over 7fh (table 17) of ipgl/r regist ers (04h, 05h) is ignored during alc operation. after alc is disabled, the ipga changes to the last written data by zero-crossing or time-out. in case of writing to the datt area (08h, 09h), the datt changes even if alc is enabled. ? output volume the AK5366VR includes two independent channel digital volumes (datt) with 144 levels at 0.5db steps located behind the adc. when changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. the data must not be written over 90h. attl/r7-0 attenuation 8fh +8.0db 8eh +7.5db : : 81h +1.0db 80h +0.5db 7fh 0db default 7eh ? 0.5db 7dh ? 1.0db : : 02h ? 62.5db 01h ? 63db 00h mute ( ? ) table 11. datt code table
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 24 - ? alc operation [1] alc limiter operation when the alc limiter is enabled, and either lch or rch exceed the alc limiter detection level (lmth bit), the ipga value is attenuated by the amount defined in the alc limiter att step (lmat bit) automatically. then the ipga value is changed commonly for l/r channels. when the zelmn bit = ?1?, the timeout period is set by the ltm1-0 bits. the opera tion for attenuation is done continuously until the input signal level becomes the alc limite r detection level (lmth bit) or less. if the alc bit does not change into ?0? or the alc pin does not change into ?l? after completing the attenuation, the attenuation operation repeats until the input signal level equals or ex ceeds the alc limiter detection level (lmth bit). when the zelmn bit = ?0?, the timeout period is set by the ztm1-0 bits. this enable s the zero-crossing attenuation function so that the ipga value is attenuated at the zero-detect points of the waveform. when fr bit = ?1?, the alc operation corresponds to the impul se noise in additional to the normal alc operation. then if the impulse noise is supplied at zelm n bit = ?0?, the alc operation becomes th e faster period than a set of ztm1-0 bits. in case of zelmn bit = ?1 ?, it becomes the same period as ltm1-0 bits . when fr bit = ?0?, the alc operation is the normal alc operation. [2] alc recovery operation the alc recovery refers to the amount of time that the AK5366VR will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. the alc recovery operation uses the wtm1-0 bits to define the wait period used after completing an alc limiter operation. if the input signal does not exceed the ?a lc recovery waiting counter reset level?, the alc recovery operation starts. the ipga value increases automatically during this operation up to the reference level (ref7-0 bits). the alc recovery operation is done at a period set by the wtm1-0 bits. zero crossing is detected during wtm1-0, the alc recovery operation waits wtm1-0 period and the next recovery operation starts. during the alc recovery operation, when input signal level exceeds the alc limiter detection level (lmth bit), the alc recovery operation changes immediately into an alc limiter operation. in the case of ?(recovery waiting counter reset level) input signal < limiter detection level? during the alc recovery operation, the wait timer for the alc recovery operation is re set. therefore, in the case of ?(recovery waiting counter reset level) > input signal?, the wait timer for the alc recovery operation starts. when the impulse noise is input at fr bit = ?1?, the alc recovery operation becomes faster than a normal recovery operation. when the fr bit = ?0?, the alc recovery operation is done by normal period.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 25 - [3] alc level diagram (1) alc=off figure 9 and 10 show the level diagram example at alc=off. in figure 9, input att is ? 12db. input 4vrms 2vrms att ipga adc 0dbfs -12db -12db -12db 1vrms -12db +6db +12db figure 9. alc level diagram example (alc=off) in figure 10, input att is ? 6db. input 2vrms 1vrms att ipga adc 0dbfs -6db -6db -6db 0.5vrms -6db +6db +12db figure 10. alc level diagram example (alc=off)
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 26 - (2) alc=on figure 11 and 12 show the level diagram example at alc=on. in figure 11, input att is ? 12db and ref7-0 bits are ?8ch?. input 4vrms 2vrms att alc adc -12db -12db -12db 1vrms -12db 0.5vrms -0.5db -0.5dbfs -6dbfs -12dbfs 0dbfs +5.5db +6db 0.25vrms figure 11. alc level diagram exam ple (alc=on, lmth bit=?0?) in figure 12, input att is ? 6db and ref7-0 bits are ?8ch?. input 2vrms 1vrms att alc adc -6db -6db 0.5vrms -6db 0.25vrms -6db -0.5db -0.5dbfs -6dbfs 0dbfs +5.5db +6db -12dbfs figure 12. alc level diagram example (alc=on, lmth=?0?)
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 27 - [4] example of alc operation the following registers should not be changed during the alc operation. ? ltm1-0, lmth, lmat, wtm1-0, ztm1-0, ratt, ref7-0, zelmn bits ? the ipga value of lch becomes the star t value if the ipga value is different with lch and rch when the alc starts. ? writing to the area over 80h (table 17) of ipgl/r registers (04h, 05h) is ignored during alc operation. after alc is disabled, the ipga changes to the last written data by zero-crossing or time-out. in case of writing to the datt area (table 11) of datt registers (08h, 09h), the datt changes even if alc is enabled. manual mode finish alc mode and return to manual mode finish alc mode? ye s no set (sel2-0 bits or sel2-0 pins) wr (ztm1-0, wtm1-0, ltm1-0) wr (lmat, ratt, lmth) wr (ref7-0) wr (ipga7-0) alc operation wr (alc = ?0?) wr (alc = ?1?) (1) (2) (1) (2) pdn = ?l? ?h? alc o p eration alc off (wr: alc = ?0?) note : wr : write figure 13. registers set-up sequence at alc operation (1): enable soft mute (2): disable soft mute note : after alc operation is disabled, the ipga changes to the last written data during or before alc operation.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 28 - [5] ipga value before and after alc operation after alc operation is disabled, the ipga changes to the last written data during or before alc operation. [operation example 1] 1. set ipga = +12db at alc=off. datt portion is set to 0db internally. 2. alc=on after soft mute is enabled. 3. disable the soft mute. 4. during alc operation. the ipga changes from ? 9.5db to the value set by ref7-0 bits. 5. alc=off after soft mute is enabled. 6. disable the soft mute. the ipga return to +12db automatically. [operation example 2] 1. set ipga = +12db at alc=off. datt portion is set to 0db internally. 2. alc=on after soft mute is enabled. 3. disable the soft mute. 4. during alc operation. when the datt portion is set to ? 10db, the ipga changes from ? 19.5db to the value set by ref7-0 bits. 5. alc=off after soft mute is enabled. 6. disable the soft mute. the ipga setting is ? 10db. ? soft mute operation soft mute operation is performed in the digital domain of the adc output. soft mute can be controlled by smute bit or smute pin. the smute bit and smute pin are ored between pin and register. when smute bit goes ?1? or smute pin goes ?h?, the adc output data is attenuated by ? within 1028 lrck cycles. when the smute bit re turned ?0? and smute pin goes ?l? th e mute is cancelled and the output attenuation gradually changes to datt value within 1028 lrck cycles. if the soft mute is cancelled before mute state after starting of the operation, the attenuation is discontinued and returned to datt value. soft mute function and digital volume are common. smute a ttenuation datt level - gd gd (1) (2) (3) sdto figure 14. soft mute function (1) the output signal is attenuated by ? within 1028 lrck cycles (1028/fs). (2) digital output delay from the analog input is called the group delay (gd). (3) if the soft mute is cancelled before the mute, the attenuation is discontinued and returned to datt value.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 29 - ? chip address in case of 3-wire control mode, the chip address is fixed to c1 bit = ?1? and c0 bit = ?0?. table 12 shows the relationship between chip address (c1-0 bits) and cad1 pin in i 2 c-bus control mode. cad1 pin c1 bit c0 bit l 0 fixed to ?1? h 1 fixed to ?1? table 12. chip address in i 2 c-bus control note : c1 bit should match with the input level of cad1 pin. ? serial control interface (1) 3-wire serial contro l mode (i2c pin = ?l?) internal registers may be written by usi ng the 3-wire p interface pins (csn, ccl k and cdti). the data on this interface consists of a chip address (2bits, fixed to ?10?), read/write (1bit, fixed to ?1?, write only), register address (msb first, 5bits) and control data (msb first, 8bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. after a low-to-high transition of csn, data is latched for write operations. the clock speed of cclk is 5mhz (max). the value of internal registers is initialized at pdn pin = ?l?. csn cclk cdti 0 123456789101112131415 c1 c0 r/w a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 c1 - c0 : chip address (c1="1", c0="0") r/w : read / write (fixed to "1" : write only) a4 - a0 : register address d7 - d0 : control data figure 15. serial control i/f timing
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 30 - (2) i 2 c-bus control mode (ctrl pin = ?h?) the AK5366VR supports the standard-mode and the first-mode i 2 c-bus system (max: 400khz). (2)-1. write operations figure 16 shows the data transfer sequence for the i 2 c-bus mode. all commands are pr eceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition (figure 22). after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit that is a data direction bit (r/w). the most significant five bits of the slave addre ss are fixed as ?00100?. the next one bit are cad1 (device address bits). this one bit identify the specific device on the bus. the hard-wired input pin (cad1 pin) set these device address bits (figure 17). if the slave address matches th at of the AK5366VR, the AK5366VR generates an acknowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse (figure 23). a r/w bit value of ?1? indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the AK5366VR. the format is msb first, and those most significant 3-bits are fixed to zeros (figure 18). the data after the second byte contains control data. the format is msb first, 8bits (figure 19). the AK5366VR generates an acknowledge after each byte has been recei ved. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 22). the AK5366VR can perform more than one byte write operati on per sequence. after receipt of the third byte the AK5366VR generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is tran sferred. after receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 0dh prior to generating the stop c ondition, the address counter will ?roll ove r? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl lin e is low (figure 24) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 16. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 cad1 1 r/w (cad1 should match with cad1 pin.) figure 17. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 18. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 19. byte structure after the second byte
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 31 - (2)-2. read operations set the r/w bit = ?1? for the read operation of the AK5366VR. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cy cle after the receipt of the first data word. after receiving each data packet the inte rnal 5-bit address counter is increm ented by one, and the next data is automatically taken into the next address. if the address exceeds 0dh prior to generating a stop condition, the address counter will ?roll over? to 00h and th e previous data will be overwritten. the AK5366VR supports two basic read operations: current address read and random address read. (2)-2-1. current address read the AK5366VR contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the AK5366VR generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but instead generates a stop condition, the AK5366VR ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 20. current address read (2)-2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit set to ?1?. the AK5366VR then generates an acknowledge, 1 byte of data and increments the internal a ddress counter by 1. if the master does not generate an acknowledge to the data but instead generates a stop condition, the AK5366VR ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 21. random address read
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 32 - scl sda stop condition start condition s p figure 22. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 23. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 24. bit transfer on the i 2 c-bus
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 33 - ? control by pin and bit function pin bit input selector sel2-0 pin ?lll? : lin1/rin1 ?llh? : lin2/rin2 ?lhl? : lin3/rin3 ?lhh? : lin4/rin4 ?hll? : lin5/rin5 sel2-0 bit ?000? : lin1/rin1 ?001? : lin2/rin2 ?010? : lin3/rin3 ?011? : lin4/rin4 ?100? : lin5/rin5 soft mute smute pin (internal pull-down) ?l? : normal operation ?h? : soft muted smute bit ?0? : normal operation ?1? : soft muted table 13. pin and bit control note : the sel2-0 pins should be fixed to ?lll? if the AK5366VR is controlled by the s el2-0 bits, because the setting of the sel2-0 pins are prior to the sel2-0 bits setting. soft mute is ored between pin and register. ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down & reset control 0 0 0 0 0 mckpd mckac pwn 01h input selector control 0 0 0 0 0 sel2 sel1 sel0 02h clock & format control 0 0 0 0 dif cks1 cks0 smute 03h timer select 0 0 ltm1 ltm0 ztm1 ztm0 wtm1 wtm0 04h lch ipga control ipgl7 ipgl6 ipg l5 ipgl4 ipgl3 ipgl2 ipgl1 ipgl0 05h rch ipga control ipgr7 ipgr6 ipgr5 ipgr4 ipgr3 ipgr2 ipgr1 ipgr0 06h alc mode control 1 0 0 zelmn alc fr lmth ratt lmat 07h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 08h lch datt control attl7 attl6 attl5 attl7 attl7 a ttl7 attl7 attl0 09h rch datt control attr7 attr 6 attr5 attr4 attr3 attr2 attr1 attr0 0ah lch peak hold low byte phl7 phl6 phl5 phl4 phl3 phl2 phl1 phl0 0bh lch peak hold high byte phl15 phl14 phl13 phl12 phl11 phl10 phl9 phl8 0ch rch peak hold low byte phr7 phr6 phr5 phr4 phr3 phr2 phr1 phr0 0dh rch peak hold high byte phr15 phr14 phr13 phr12 phr11 phr10 phr9 phr8 pdn pin = ?l? resets the registers to their default values. note: unused bits must contain a ?0? value. note: only write to address 00h to 09h. note: 3-wire serial control does not support read function. i2c control supports read function.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 34 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down & reset control 0 0 0 0 0 mckpd mckac pwn r/w rd rd rd rd rd r/w r/w r/w default 0 0 0 0 0 0 0 1 pwn: power down control 0 : power down. all registers are not initialized. 1 : normal operation (default) ?0? powers down all sections and then both ipga and adc do not operate. the contents of all register are not initialized and enabled to write to the registers. when mclk and lrck are changed, it is not necessary to reset by the pdn pin or pwn bit because the AK5366VR builds in reset-free circuit. however, it can be reduced the noise by reset. mckac: master clock input mode select 0 : cmos input (default) 1 : ac coupling input mckpd: mclk input buffer control 0 : enable (default) 1 : disable when mclk input with ac coupling is stopped, mckpd bit should be set to ?1?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h input selector control 0 0 0 0 0 sel2 sel1 sel0 r/w rd rd rd rd rd r/w r/w r/w default 0 0 0 0 0 0 0 0 sel2-0: input selector (see table 6) initial values are ?000?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h clock & format control 0 0 0 0 dif cks1 cks0 smute r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 smute: soft mute control 0 : normal operation (default) 1 : sdto outputs soft-muted. cks1-0: master clock frequency select (see table 2) initial values are ?00?. dif: audio interface format (see table 4) initial values ar e ?0? (24bit, msb first).
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 35 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h timer select 0 0 ltm1 ltm0 ztm1 ztm0 wtm1 wtm0 r/w rd rd r/w r/ w r/w r/w r/w r/w default 0 0 1 0 1 0 1 1 wtm1-0: alc recovery waiting time (see table 14) a period of recovery operation when any limiter operation does not occur during the alc operation. wtm1 wtm0 alc recovery operation waiting period @fs=48khz 0 0 288/fs 6ms 0 1 1152/fs 24ms 1 0 2304/fs 48ms 1 1 4608/fs 96ms default table 14. alc recovery waiting time ztm1-0: zero crossing timeout (see table 15) when the ipga of each l/r channels perform zero cr ossing or timeout independently, the ipga value is changed by the p write operation, alc recove ry operation or alc limiter operation (zelmn bit = ?0?). ztm1 ztm0 zero crossing timeout period @fs=48khz 0 0 288/fs 6ms 0 1 1152/fs 24ms 1 0 2304/fs 48ms default 1 1 4608/fs 96ms table 15. zero crossing timeout ltm1-0: alc limiter period (see table 16) when zelmn bit = ?1?, the ipga value is changed immediately. when the ipga value is changed continuously, the change is done by the period set by the ltm1-0 bits. ltm1 ltm0 alc limiter operation period @fs=48khz 0 0 3/fs 63 s 0 1 6/fs 125 s 1 0 12/fs 250 s default 1 1 24/fs 500 s table 16. alc limiter period
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 36 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h lch ipga control ipgl7 ipgl6 i pgl5 ipgl4 ipgl3 ipgl2 ipgl1 ipgl0 05h rch ipga control ipgr7 ipgr6 ipgr5 ipgr4 ipgr3 ipgr2 ipgr1 ipgr0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 0 0 0 0 0 0 0 ipgl/r7-0: input pga & digital volume control (see table 17) initial values are ?80h?. the data must not be written under 80h. writing to the area over 7fh (table 17) of ipgl/r registers (04h, 05h) is ignored during alc operation. after alc is disabled, the ipga changes to the last written data by zero-crossing or time-out. in case of writing to the datt area (table 11) of datt registers (08h, 09h), the datt changes even if alc is enabled. data (hex) gain (db) step width (db) a4h +18 0.5 : : 0.5 9eh +15 0.5 : : 0.5 98h +12 0.5 97h +11.5 0.5 96h +11 0.5 : : 0.5 82h +1.0 0.5 81h +0.5 0.5 80h 0 - ipga analog volume with 0.5db step table 17. ipga code table
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 37 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h alc mode control 1 0 0 zelmn alc fr lmth ratt lmat r/w rd rd r/w r/ w r/w r/w r/w r/w default 0 0 1 0 1 0 0 0 lmat: alc limiter att step (see table 18) during the alc limiter operation, when either lch or rc h exceeds the alc limiter detection level set by lmth bit, the number of steps attenuated from the current ipga va lue is set. for example, when the current ipga value is 94h and the lmat bit = ?1?, the ipga transition to 92h when the alc limiter operation starts, resulting in the input signal level being attenuated by 1db (=0.5db x 2). lmat att step 0 1 default 1 2 table 18. alc limiter att step ratt: alc recovery gain step (see table 19) during the alc recovery operation, the number of step s changed from the current ipga value is set. for example, when the current ipga value is 82h and ratt b it = ?1? is set, the ipga changes to 84h by the alc recovery operation and the out put signal level is gained up by 1db (= 0.5db x 2). when the ipga value exceeds the reference level (ref7-0 bits), the ipga value does not increase. ratt gain step 0 1 default 1 2 table 19. alc recovery gain step lmth: alc limiter detection level / recovery waiting counter reset level (see table 20) the alc limiter detection level and the alc recovery counter reset level may be offset by about 2db. lmth alc limiter detection level alc recovery waiting counter reset level 0 alc output ? 0.5dbfs ? 0.5dbfs > alc output ? 2.5dbfs default 1 alc output ? 2.0dbfs ? 2.0dbfs > alc output ? 4.0dbfs table 20. alc limiter detection level / recovery waiting counter reset level fr: alc fast recovery 0 : disable 1 : enable (default) when the impulse noise is input, the alc recovery opera tion becomes faster than a normal recovery operation. alc: alc enable flag 0 : alc disable (default) 1 : alc enable zelmn: zero crossing enable flag at alc limiter operation 0 : enable 1 : disable (default) when the zelmn bit = ?0?, the ipga of each l/r channel perform a zero crossing or timeout independently. the zero crossing timeout is the same as the alc r ecovery operation. when the zelmn bit = ?1?, the ipga value is changed immediately. the al c limiter period can be set up by a ztm 1-0 bits when zelmn bit = ?0?, it can be set up by a ltm1-0 bits when zelmn bit = ?1?
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 38 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 0 0 0 1 1 1 0 ref7-0: reference value at alc recovery operation (see table 21) during the alc recovery operation, if the ipga value exceeds the setting reference value by gain operation, then the ipga does not become larg er than the reference value. the ref7-0 bits should not be set up except for table 21. data (hex) gain (db) a4h +18.0 : : 90h +8.0 8fh +7.5 8eh +7.0 default 8dh +6.5 : : 89h +4.5 : : 81h +0.5 80h 0 table 21. reference value at alc recovery operation addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h lch datt control attl7 attl6 attl5 attl4 attl3 a ttl2 attl1 attl0 09h rch datt control attr7 attr 6 attr5 attr4 attr3 attr2 attr1 attr0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 1 1 1 1 1 1 1 attl/r7-0: digital output vol ume control (see table 11) initial value is ?7fh?. the data must not be written over 90h. when pdn pin = ?l?, attl/r7-0 bits are initialized ?7fh?. when pwn bit = ?0?, the datt holds the last setting value. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah lch peak hold low byte phl7 phl6 phl5 phl4 phl3 phl2 phl1 phl0 0bh lch peak hold high byte phl15 phl14 phl13 phl12 phl11 phl10 phl9 phl8 0ch rch peak hold low byte phr7 phr6 phr5 phr4 phr3 phr2 phr1 phr0 0dh rch peak hold high byte phr15 phr14 phr13 phr12 phr11 phr10 phr9 phr8 r/w rd default 0 0 0 0 0 0 0 0 phl15-0: lch peak hold low/high byte phr15-0: rch peak hold low/high byte the AK5366VR includes the peak hold circuit. the peak is held l/r audio data independently. these registers are reset by reading 8bit of msb, reading 8bit of both msb and lsb should be continuity controlled by reading in order of 8bit of msb from lsb. after reading 8bit of lsb the last, 8bit of msb is lost by reading 8bit of lsb the last. the output value is the absolute valu e. full scale is ?ffffh?. these registers are reset by pdn pin = ?l? or pwn bit = ?0?.
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 39 - system design figure 25 shows the system connection diagram. an evalua tion board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. ? master mode, 3-wire control (i2c pin = ?l?) lin5 1 2 3 4 5 6 7 8 9 11 12 test1 lin4 test2 lin3 test3 lin2 test4 lin1 lopin lout top view nc rin5 48 47 46 test8 rin4 45 44 42 41 43 38 37 40 test7 rin3 test6 rin2 test5 rin1 m/s i2c 47k 1 47k 1 47k 1 47k 1 47k 1 24k 4.7 47k 1 47k 1 47k 1 47k 1 47k 1 reset dsp and up 36 35 34 33 32 31 30 29 28 27 26 csn/cad1 cclk/scl cdti/sda sel2 sel1 sel0 smute tvdd pdn mclk lrck analog supply 4.75 ~ 5.25v ipgar 14 rout 15 ropin 16 17 18 avdd 19 avss 20 vcom 21 dvss 22 23 dvdd 24 sdto 0.1 10 2.2 0.1 24k 4.7 10 0.1 digital supply 3.0 ~ 5.25v nc 0.1 10 10 nc 13 ipgal 25 bick 39 nc note: - avss and dvss of the AK5366VR should be distributed separately from the ground of external digital devices (mpu, dsp etc.). - when lout/rout drives a capacitive load, resi stors should be added in series between lout/rout and capacitive load. - all digital input pins should not be left floating. - m/s pin should be connected to avdd or avss. figure 25. typical connection diagram
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 40 - 1. grounding and power supply decoupling the AK5366VR requires careful attention to power s upply and grounding arrangements. avdd, dvdd and tvdd are usually supplied from the analog supply in the system. alternatively if avdd, dvdd and tvdd are supplied separately, the power up sequence is not critical. avss and dvss of the AK5366VR must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK5366VR as possible, with the small value ceramic capacitor being the closest. 2. voltage reference inputs the differential voltage between avdd and avss sets the anal og input range. vcom is a signal ground of this chip. an electrolytic capacitor 2.2f parallel with a 0.1f ceramic capacitor attached to vc om pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vref and vcom pins in order to avoid unwanted coupling into the AK5366VR. 3. analog inputs an analog input of AK5366VR is single-ended input to pre-amp through the external resistor. for input signal range, adjust feedback resistor so that pre-amp output may become the input range (typ. 0.2 x avdd vrms) of ipga (ipgal, ipgar pin). between the pre-amp output (lout, rout pin) and the ipga input (ipgal, ipgar pin) is ac coupled with capacitor. when the impedance of ipgal/r pins is ?r? and the capacitor of between the pre-amp output and the ipga input is ?c?, the cut-off frequency is fc = 1/(2 rc). the adc output data format 2?s compliment. the internal hpf removes the dc offset. the AK5366VR samples the analog inputs at 64fs. the digital filter rejects noise above the stop band except for multiples of 64fs. the AK5366VR includes an anti-aliasing f ilter (rc filter) to attenuate a noise around 64fs. 4. attention to the pcb wiring lin1-5 and rin1-5 pins are the summing nodes of the pre-amp. attention should be given to avoid coupling with other signals on those nodes. this can be accomplis hed by making the wire lengt h of the input resistors as short as possible. the same theory also applies to the lopin/ropin pins and feedback resistors; keep the wire length to a minimum. unused input pins among lin1-5 and rin1-5 pins should be left open. when external devices are connected to lout and rout pin, the input impedance of an external device which the lout and rout pins can drive is min 6.3k ? .
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 41 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48 p in lqfp ( unit:mm ) 0.10 37 24 25 36 0.16 0.07 1.40 0.05 0.13 0.13 1.70ma x 0 10 0.10 0.5 0.2 0.5 m ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatme nt: solder (pb free) plate
asahi kasei [AK5366VR ] ms0526-e-00 2006/07 - 42 - marking AK5366VR xxxxxxx 1 xxxxxxx : date code identifier (7 digits) date (yy/mm/dd) revision reason page contents 06/07/20 00 first edition important notice ? these products and their specific ations are subject to change wi thout notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concer ning their current status. ? akm assumes no liability for infringement of any pat ent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or syst ems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the expre ss written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expec ted to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to f unction or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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